Analysis of Power Dissipation and Delay in 6T and 8T SRAM Using Tanner Tool
Publication Date : 13/04/2016
Due to growth of technology scaling, at low-voltage operation, Static Random Access memory (SRAM) bit-cells suffer from large failure rate and power consumption is also more in scaling technology, In this paper we work on CMOS SRAM, To decrease the power dissipation during the Write operation because the write operation consumes more power. The charging of bit lines and discharging of bit lines dissipate more power during write “1” and write “0” operation. 8T SRAM cell includes two more transistors (NMOS) for appropriate charging and discharging the bit lines. The results of 8T SRAM cell are taken on different frequencies at power supply of 1.5 Volt. In the circuit we use the 130 nm technology, and the supply voltage of 1.5 Volt. Finally the results are compared with Conventional 6T SRAM. The power dissipated in low power 8T (transistors) SRAM cell is reduced in comparison to conventional 6T SRAM cell.
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