International Journal of Recent Trends in Engineering & Research

online ISSN

TLA for preemptive scheduling

Publication Date : 30/09/2017

DOI : 10.23883/IJRTER.2017.3438.1FMJI

Author(s) :

Dr.M.Shyam sundar.

Volume/Issue :
Volume 3
Issue 9
(09 - 2017)

Abstract :

These designs pose significant challenges to the channel management scheme, flow, and tools. This paper introduces several test logic architectures that facilitate preemptive test scheduling for SC circuits with embedded deterministic test-based test data compression. The same solutions allow efficient handling of physical constraints in realistic applications. This paper presents several techniques employed to resolve problems surfacing when applying scan bandwidth management to large industrial multicore system-on-chip (SC) designs with embedded test data compression. A detailed case study is illustrated herein with a variety of experiments allowing one to learn how to tradeoff different architectures and test-related factors. Finally, state-of-the-art SC test scheduling algorithms are architected accordingly by making provisions for: setting up time-effective test configurations; optimization of SC pin partitions; allocation of core-level channels based on scan data volume; and more flexible core-wise usage of automatic test equipment channel resources.

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