An Efficient Design of Low Power and Low Leakage Class-AB CMOS Amplifier using Gating Technique
Publication Date : 30/01/2018
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A rail-to-rail class-AB CMOS buffer amplifier is proposed in this paper to drive large capacitive loads. A new technique is used to reduce the leakage power of class-AB CMOS buffer circuits without affecting dynamic power dissipation .The name of applied technique is Transistor Gating Technique, which gives the high speed buffer with the reduced low power dissipation , low leakage and reduced area also. The proposed buffer is simulated at 180nm CMOS technology and the circuit is operated at 1.65V supply with Cadence software. This analog circuit is performed with reduced performance degradation as well as high current driving capability for the large input voltages. The proposed paper is achieved very high speed with very low propagation delay.
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