Area and Power efficient Design of edge triggered D Flip Flop using GDI Technique
Publication Date : 26/01/2018
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Increasing demand of portable devices creating larger scope in the field of Low power device design. VLSI designing of the efficient circuits is aiming towards the devices consuming less power and produces less delay with capability to operate in wider range of frequencies .This paper presents a single edge triggered D-Flip flop configuration for optimizing the power consumption by using gate diffusion input technique using the gate clocking methodology. A further 1.38% optimization is obtained by using this method. Properties of implemented circuit are discussed and simulation results are observed using cadence tool.
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