Braun’s Multiplier Implementation using Ripple Carry Adder, Kogge-Stone Adder and 14-transistor novel ADDER.
Publication Date : 30/01/2018
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Developing an Application Specific Integrated Circuits (ASIC‟s) willcost very high, circuits should be proved and then it would be optimized before implementation. Multiplication, which is the basic building block for several DSP processors, Image processing and many other , can be easily done by the implementation of Braun‟s Multiplier using different Adder Cells. The implementation of this multiplier and its bypassing techniques is done using Cadence(Back End). There is the reduction in the factors like delay LUT‟s, number of slices used. The Braun‟s Multiplier uses the full adder block and fast addition method so that we are reducing the delay. In the Row and Column bypassing method we used ripple carry adder, kogge-stone adder and 14-transistor novel adder. The structure consists of array of AND gates and adders arranged in the iterative manner. The proposed system “BRAUN‟S MULTIPLIER IMPLEMENTATION USING RIPPLE CARRY ADDER, KOGGE STONE ADDER AND 14-TRANSISTOR NOVEL ADDER” is implemented in 45nm technology using cadence virtuoso tool. The circuit schematic designed and the circuits are simulated for functionality verification.
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