International Journal of Recent Trends in Engineering & Research

online ISSN

Design of Low-Latency Virtual-Channel Routers for Network on Chip Router

Publication Date : 26/01/2018


DOI : 10.23883/IJRTER.CONF.20171225.003.JGQ8Y


Author(s) :

D.DAYAKAR RAO , Dr.P.V.NAGANJANEYULU.


Conference Name :
RECENT ADVANCES IN ELECTRONICS AND COMMUNICATION ENGINEERING-2017



Abstract :

The on-chip communication requirements of many systems are best served through the deployment of a regular chip-wide network. This paper presents the design of a low-latency on-chip network router for such applications. We remove control overheads (routing and arbitration logic) from the critical path in order to minimise cycle-time and latency. Simulations illustrate that dramatic cycle time improvements are possible without compromising router efficiency. Furthermore, these reductions permit flits to be routed in a single cycle, maximising the effectiveness of the router’s limited buffering resources.


No. of Downloads :


Indexing

License

Traffic Stats

Total Visits : 6,144