International Journal of Recent Trends in Engineering & Research

online ISSN

Design of Low Power and High Speed 4-Bit Ripple Carry Adder Using area efficient full adder cell in 180nm CMOS Process Technology

Publication Date : 30/01/2018


DOI : 10.23883/IJRTER.CONF.20171225.068.MBE6A


Author(s) :

Y.Devendar Reddy , S.Madhu.


Conference Name :
RECENT ADVANCES IN ELECTRONICS AND COMMUNICATION ENGINEERING-2017



Abstract :

Adders are basic components of digital design and necessary part of any digital signal Processing(DSP) architecture and microprocessors. In this paper design of a 4-bit ripple carry adder is proposed using a novel 18-transistor CMOS transmission gate full adder cell. The main objective is to reduce area by decreasing the transistor count compared with the ripple carry adder using conventional full adder. The design is implemented using Cadence Virtuoso schematic editor and simulated using Cadence Virtuoso analog design environment at 180nm CMOS process technology. The simulation results of the ripple carry adder using the proposed full adder cell are compared with ripple carry adder using conventional full adder cell in terms of transistor count, delay and power. The number of transistors is reduced from 28 in conventional full adder to 18 in the proposed transmission gate full adder. As a result the proposed 4-bit ripple carry adder with 72 transistors is efficient in terms of area.


No. of Downloads :

6


Indexing

License

Traffic Stats

Total Visits : 6,139