International Journal of Recent Trends in Engineering & Research

online ISSN

Design of Reconfigurable Pseudorandom Test Pattern Generator for BSIT

Publication Date : 30/01/2018


DOI : 10.23883/IJRTER.CONF.20171225.089.DNOGJ


Author(s) :

P.SINDHUJA , S.SRINIVAS RAO , B.N.MANJU BHARGAVI.


Conference Name :
RECENT ADVANCES IN ELECTRONICS AND COMMUNICATION ENGINEERING-2017



Abstract :

This paper describes a low-power (LP) programmable generator producing pseudorandom test patterns with desired toggling levels and enhanced fault coverage gradient compared with the best-to-date built-in-self-test(BIST)-based pseudorandom test pattern generators. It is comprised of a linear finite state machine driving an appropriate phase shifter, and it comes with a number of features allowing this device to produce binary sequences with preselected toggling (PRESTO) activity. We introduce a method to automatically select several controls of the generator offering easy and precise tuning. State of the development in the semiconductor manufacturing process, integrated chip design methodology, availability of thousand plus pin integrated circuit packaging options and efficient IC test techniques have contributed immensely towards the integration of entire system on a chip. The System-On-Chip (SOC) devices can have multiple microprocessors, various types of memories such as SRAM, Flash, Digital Signal Processors, many IP blocks and user defined logics. Numerous SOC test techniques have been innovated in the last decade to test complex mixed signal systems on a chip in a cost effective manner. Test industry has made complete strides in developing new automated test equipment which can analog components, test logic, memory of the chip through external interface to the IC. Here with the experimental results with presence of switching activity in PRESTO, Fully operational PRESTO power comparison is performed with LP Decompressor.


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