International Journal of Recent Trends in Engineering & Research

online ISSN

EFFICIENT RECODING USING FAM

Publication Date : 30/01/2018


DOI : 10.23883/IJRTER.CONF.20171225.093.K5OPM


Author(s) :

C.Gouthami , P.V Kusuma.


Conference Name :
RECENT ADVANCES IN ELECTRONICS AND COMMUNICATION ENGINEERING-2017



Abstract :

Complex arithmetic operations are widely used in Digital Signal Processing (DSP) applications. In this work, we focus on optimizing the design of the fused Add-Multiply (FAM) Operator for increasing performance. We investigate techniques to implement the direct recoding of the sum of two numbers in its Modified Booth (MB) form. We introduce a structured and efficient recoding technique and explore three different schemes by incorporating them in FAM designs. In proposed, we focus on Multiply unit which implement the operation. The conventional design of the operator requires complex algothmic process. The drawback of using an this multiplier is that it inserts a significant delay in the critical path of the AM. As there are carry signals to be propagated inside the adder, the critical path depends on the bit-width of the inputs. In order to decrease this delay, a SPST adder can be used which, however, the increases the area occupation and the power dissipation. Comparing them with the FAM designs which use existing recoding schemes, the proposed technique yields considerable reductions in terms of critical delay, hardware complexity of the FAM unit by using Modified Wallace Tree Multiplication. The FAM Architecture is implemented by Verilog Hardware Description Language and it is synthesized by Xilinx tool.


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