International Journal of Recent Trends in Engineering & Research

online ISSN

FPGA Implementation of Borrow Save Adder Under Threshold Voltage Variability

Publication Date : 22/03/2019

DOI : 10.23883/IJRTER.CONF.20190322.021.NC59N

Author(s) :

P.Monika , M.Gowsalya , N.Naga sowmiya.

Conference Name :
1st International Conference on New Scientific Creations in Engineering and Technology - 2019

Abstract :

Adder is a building block of all arithmetic units used in processors. The performances of adders are evaluated on the basis of power consumption, energy consumption and delay. In this approach the Borrow Save Adder (BSA) is designed with minimum delay under low threshold voltage and it is compared with Ripple Carry Adder (RCA). It presents a solution for low power addition under threshold voltage variability, which successfully handles the changes of increasing threshold voltage. In addition the proposed approach demonstrates the tolerance of adder unit to variations.

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