High speed Single Symbol Error Correction Codes Based on Reed Solomon Codes using verilog
Publication Date : 30/01/2018
Conference Name :
To keep away from information debasement, error correction codes (ECCs) are broadly used to secure recol-lections. ECCs present a postpone punishment in getting to the information as encoding or translating must be performed. This restrains the utilization of ECCs in rapid recollections. This has prompted the utilization of basic codes, for example, single error correction double error detection (SEC-DED) codes. In any case, as innovation scales multiple cell upsets (MCUs) turn out to be more typical and cutoff the utilization of SEC-DED codes unless they are joined with interleaving. A comparative issue happens in a few sorts of recollections like DRAM that are ordinarily gathered in modules made out of a few gadgets. In those modules, the insurance against a gadget disappointment as opposed to detached piece blunders is additionally alluring. In those cases, one alternative is to utilize further developed ECCs that can remedy numerous piece blunders. The primary challenge is that those codes ought to limit the deferral and region punishment. Among the codes that have been considered for memory assurance are Reed-Solomon (RS) codes. These codes depend on non-paired images and in this way can redress different piece blunders. In this paper, single image blunder adjustment codes based on Reed-Solomon codes that can be executed with low deferral are proposed also, assessed. The outcomes demonstrate that they can be executed with a generously bring down postponement than customary single blunder adjustment RS codes.
No. of Downloads :